In a design stage of the semiconductor integrated circuit, whether or not all terminals are definitely connected to fixed potentials, i.e., a power supply potential (VDD), an earth potential (VSS) or internal potentials that are a plurality of internal potentials generated inside the integrated circuit are verified (hereinafter referred to as “floating check”).
In the floating check, after a net list showing the connection state of a logic circuit from a logic circuit diagram prepared by a CAD tool is generally extracted, a circuit simulation is executed by using an electronic design automation (EDA) tool. In this case, a transistor is completely turned ON to judge whether or not a current is conducted to fixed potentials through the transistor. Although the criteria for detecting floating error terminals are different, depending upon EDA tools, in almost circuit simulators, whether or not there is a path that is conducted to a fixed potential judges the existence or nonexistence of the floating error terminals (see Japanese Patent application Laid Open No. 1993-74948 and Japanese Patent application Laid Open No. 2000-293555).